Alpha particles are helium (He) nuclei that comprise two protons and two neutrons. Alpha particles, which are often emitted from larger atoms as a result of radioactive decay, can penetrate the die surface of an electronic device, creating a cloud of electron-hole pairs along the track of alpha particles. An alpha particle emitted from the integrated circuit (IC) materials such as 210Pb has about 5.3 MeV of energy, and can travel about 25 um into the silicon. As a result, dynamic random access memory (DRAM) storage regions such as potential wells can collect sufficient number of minority carriers to change the stored state of a memory cell. Diffusion regions and sense amplifiers are also sensitive to the penetrating alpha particles.
The sensitivity of electronic devices to radiation can be described in terms of the soft-error rate (SER) measured in number of failures per bit-hour. SER generally refers to the transient single-cell upsets caused by the penetration of high-energy particles, because the carriers generated by these particles can cause individual bits to be upset. The soft errors may result in loss of data, but will not cause physical damage to the device. Although soft errors can be reset or reprogrammed, a temporary loss of data nevertheless may have a serious consequence to the system operation. For terrestrial systems, there are two common radiation mechanisms that cause SER reliability problems: the alpha-particles from radioactive contaminants in the chip and the package material, and cosmic rays. Many memory chips need to specify their estimated alpha-particle SER, based on the alpha-particle fluxes from ceramic packages and lead-based connectors. The soft errors caused by alpha particles may be controlled by the use of purified materials, while the soft errors caused by cosmic rays can be mitigated with robust chip design.
Both dynamic and static memory are volatile, but dynamic memory can lose its memory state, even with the power on, so it must be refreshed periodically. A traditional static memory cell is composed of 6 transistors, including a cross-coupled pair that toggles between the 2 states. A dynamic memory cell, on the other hand, consists of a single transistor and a storage capacitor, where a bit-line connects to the source of the transistor, and a word-line connects to the gate. The drain of the transistor device is connected directly to a planar capacitor formed by poly-silicon and oxide layers over the silicon. The state of the memory cell is determined by the presence or absence of charge on the storage node. Since the charge stored on the node of a dynamic memory cell is susceptible to leakage, it must be refreshed periodically. The refresh cycle is determined by the time it takes the charge stored in the cell to deplete to a minimal level needed for a memory cell to hold its information in the presence of alpha particles.
Three different memory cell technologies for storing the bit charge have evolved since the introduction of the 16 Mb DRAM chip: (1) the stacked capacitor with high-k dielectric layers, (2) a trench capacitor with the stored charge insulated from the substrate, and (3) a trench capacitor using p/n junction to isolate the stored charge from the substrate material. In order to maintain node capacity while reducing cell size, modern DRAM chips use 3-dimensional structures such as vertical transistors and capacitors with high-k dielectric, because smaller node capacitance often requires higher refresh rate to prevent soft-error problems. As the DRAM chip increases its size to 1 Gb, its sensitivity to radiation has also improved due to the significant reduction in DRAM volume per cell and the newer cell designs that eliminate the funneling of charge from the substrate. Since the new design has no charge stored in the silicon substrate and there is little leakage, the chip is more immune to alpha-particle hits and less susceptible to soft errors.
The single-event upset (SEU) at the chip level can be evaluated with accelerated testing by irradiating the chip with mono-energetic beams of subatomic particles. The most commonly used particles for SEU testing are heavy ions, protons and neutrons. Other particles such as electrons and high-energy photons can also be used for space applications, but they produce less ionization effects than heavy ions, protons, and neutrons. The main objective of a heavy ion test is to measure the SEU cross-section curve, which is an intrinsic characterization of the SEU sensitivity of a circuit. For heavy ions, the SEU cross section is a function of the linear energy transfer (LET), which is the average energy loss of the ion per unit track length. For protons or neutrons, the SEU cross section is a function of the particle energy. In addition, the SEU cross section is a function of device operating conditions such as supply voltage and junction temperature.
For a given particle species, the SEU cross section is defined as σSEU (E)=number of failures detected per particle fluence per number of bits, where E is the energy of the particle and particle fluence is the number of particles per unit area impinging on the test circuit. A heavy ion often refers to any ion with more than one proton in the nucleus, which includes alpha particle (a helium ion) or other heavier ions. A heavy ion causes SER due to the ionization energy deposited on a sensitive device region. This ionization energy is associated with the production of electron-hole pairs near the track of the intruding particle. Protons are also ionizing particles, which can initiate spallation reactions with semiconductor materials and cause SEU. Neutrons, on the other hand, do not cause direct ionization. When a high-energy neutron collides with a nucleus in the material around a sensitive node, a nuclear spallation reaction is initiated, which produces secondary charged fragments such as alpha particles and recoil nuclei. These secondary charged fragments hit the sensitive node and cause SEU.
Whereas the SEU cross section is an intrinsic parameter that characterizes the SEU sensitivity of a circuit, the failure-in-time (FIT) rate, or the number of failures per unit time, varies from location to location. For instance, the FIT rate due to neutrons is given by F=∫dE dφ(E)/dE σSEU(E), where dφ(E)/dE is the neutron energy differential flux in neutron number per (cm2-MeV-s)), σSEU is the neutron-induced SEU cross section, and E is the neutron energy. FIT rate due to terrestrial neutrons from cosmic rays can be computed accurately from the equation above, because σSEU can be measured, and neutron energy flux dφ(E)/dE at any location can be computed by an accurate parametric model that takes into account of the earth's altitude and geomagnetic effects.
In space programs that involve satellites or flight missions in high orbits, high-energy protons and heavy ions are the particles that cause SEUs. The failure rate due to high-energy protons can be computed by the equation above, where dφ/dE, σSEU, and E are the particle flux, cross section and energy associated with the protons. The proton flux dφ(E)/dE can be estimated by a common simulation code.
Life testing can be done by measuring the soft errors of a tester that contains hundreds of product chips, which are exposed to environmental radiation. The measurements are done under nominal operating conditions of the chips at various test locations. Although life testing provides the most realistic estimates of soft error rates, it often takes months to collect the data, which makes it difficult to use life testing as a means to predict hidden SEU problems in new technologies.
Alternatively, SEU modeling at the device and circuit level provides an important and effective evaluation that allows an engineer to discover weak spots in the early stage of design cycle. Most chips with anomalously high SEUs have been shown to suffer from weak spots such as floating bit-lines, insufficient margins on sense-amplifiers, and junctions exposed to the silicon substrate.
In U.S. Pat. No. 4,983,843, entitled “Radon detector,” a radon gas detector instrument that uses a DRAM as an alpha particle detector is described. A DRAM array devoid of an alpha particle barrier layer is constructed with no surface polyimide or other alpha-particle blocking layer to enhance the DRAM soft error rate. In addition, the DRAM refresh rate is extended to allow enough time for a particle count to be established. The DRAM is prepared for sensing by relaxing and storing “1”s in every cell. After exposing the DRAM to alpha particles and waiting a period of time for cells of the DRAM to become charged by the alpha particles, one can read the DRAM array to determine the number of charged cells in the DRAM. Since there is no provision to accelerate the detection of SER, it will take a significant period of time to collect the information. Furthermore, due to the difficulty of predicting defect-driven cell leakage, an extended refresh interval for one DRAM chip may not produce consistent SER sensitivity among a group of chips.
In U.S. Pat. No. 6,583,470, entitled “Radiation tolerant back biased CMOS VLSI,” a CMOS circuit is implemented with improved immunity to total ionizing dose radiation, radiation-induced latch up, and a single-event upset, by controlling the p-well voltage and the effective threshold voltage of the n-channel transistors, or controlling the n-well voltage and the effective threshold voltage of the p-channel transistors. Furthermore, by using the p+ and n+ guards, as well as back biasing, radiation-induced single event upsets and total ionizing dose effects can be minimized.
In U.S. Pat. No. 6,785,169, entitled “Memory cell error recovery,” the soft error rate in a semiconductor memory is improved via the use of a circuit adaptively arranged with a mirror bit to recover from a soft error. The first and mirror memory cells are configured and arranged to receive and store a same bit in response to a write operation, with the memory cells more susceptible to a bit error. For a read operation, the bits stored at the first and second memory cells are compared. If the bits are the same, the bit from the first or mirror bit is read out. If the bits are different, a bit corresponding to the more susceptible state is read out to overcome the soft errors. Although the proposed method provides a means to recover from the soft errors, it does not teach how to design a memory array to speed up the detection of soft errors.